DSD 2016

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed hardware/software system engineering, down to microarchitectures, digital circuits and VLSI techniques. It is a discussion forum for researchers and engineers from academia and industry working on state-of-the-art investigations, development and applications.

It focuses on today's and future challenges of advanced system architectures for embedded and high-performance HW/SW systems, application analysis and parallelization, design automation for all design levels, as well as, on modern implementation technologies from full custom in nanometer technology nodes, through FPGAs, to multi-core infrastructures. It covers a multitude of highly relevant design aspects from system, hardware and embedded-software specification, modeling, analysis, synthesis and validation, through system adaptability, security, dependability and fault tolerance, to system energy consumption minimization and multi-objective optimization.

Authors are kindly invited to submit their work according (but not limited) to the seven main topics of the conference main track. In addition, eight Special Sessions (with their own coordinators and subprogram committees) do also welcome contributions in specific themes of particular interest. All papers are reviewed following guidelines, quality requirements and thresholds that are common to all committees.

The 19th Euromicro Conference on Digital Systems Design will take place in Limassol, Cyprus.


Important Dates

  • Paper Submission: April 8th 2016 Extended to April 24th
  • Notification of Acceptance: May 30th 2016 Extended to June13th
  • Camera-ready Paper Due: June 27th 2016 Extended to July 1st



Call for Papers Special Sessions



Call for Papers DSD 2016 Main Track

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed hardware/software system engineering, down to microarchitectures, digital circuits and VLSI techniques. It is a discussion forum for researchers and engineers from academia and industry working on state-of-the-art investigations, development and applications.

It focuses on today's and future challenges of advanced system architectures for embedded and high-performance HW/SW systems, application analysis and parallelization, design automation for all design levels, as well as, on modern implementation technologies from full custom in nanometer technology nodes, through FPGAs, to multi-core infrastructures. It covers a multitude of highly relevant design aspects from system, hardware and embedded-software specification, modeling, analysis, synthesis and validation, through system adaptability, security, dependability and fault tolerance, to system energy consumption minimization and multi-objective optimization.

Authors are kindly invited to submit their work according (but not limited) to the seven main topics of the conference main track. In addition, eight Special Sessions (with their own coordinators and subprogram committees) do also welcome contributions in specific themes of particular interest. All papers are reviewed following guidelines, quality requirements and thresholds that are common to all committees.

You may download the CfP here: long version, short version



IMPORTANT DATES

  • Deadline for paper submission: April 8th
  • Notification of acceptance: May 30th
  • Camera ready papers: June 27th


MAIN TRACK TOPICS

  • T1: Advanced applications of embedded and cyber-physical systems
  • T2: Application analysis and parallelization for embedded and high-performance design
  • T3: Specification, modeling, verification and test for systems, hardware and embedded software
  • T4: Design and synthesis of systems, hardware and embedded software
  • T5: Systems-on-a-chip and networks-on-a-chip
  • T6: Programmable/re-configurable/adaptable architectures
  • T7: New issues introduced by emerging technologies



MAIN TOPICS DESCRIPTION

T1: Advanced applications of embedded and cyber-physical systems
Challenging and highly-demanding modern applications in (wireless) communication and networking; networked electronic media, multimedia and ambient intelligence; image and video processing; mobile systems; ubiquitous, wearable and implanted systems; military, space, avionics, measurement, control and automotive applications; wireless sensor network applications; surveillance and security; environmental, agriculture, urban, building, transportation, traffic, energy, hazard and disaster monitoring and control.

T2: Application analysis and parallelization for embedded and high-performance hardware and software design
Application profiling, characterization and bottleneck detection; application restructuring for parallelism; application parallelization, information-flow analysis, scheduling and mapping for application-specific processor; MPSoC memory and communication architecture synthesis; HW/SW co-design and algorithm/architecture matching; combined hardware/software design space exploration and HW/SW system multi-objective optimization; parallelization, scheduling and mapping of applications for (heterogeneous) processor and MPSoC architectures; re-targetable (application-specific) compilation; architectural support for compilers/programming models; performance, energy consumption and other parametric analysis for HW/SW systems; analytical modeling and simulation tools; benchmark applications, workload and benchmarking for heterogeneous HW/SW systems; virtual and FPGA-based system prototyping.

T3: Specification, modeling, analysis, verification and test for systems, hardware and embedded software
Modeling, simulation, design and verification languages; functional, structural and parametric specification and modeling; model-based design and verification; system, hardware, and embedded software analysis, simulation, emulation, prototyping, formal verification, design-for-test and testing at all design levels; dependability, safety, security and fault-tolerance issues.

T4: Design and synthesis of systems, hardware and embedded software
Quality-driven design; model-, platform- and template-based design; design-space exploration; multi-objective optimization; system, processor, memory and communication architecture design; application scheduling and mapping to platforms; application-specific circuits and processors; arithmetic, signal, vector and graphics processing units; hardware accelerators; transaction level modeling and higher-level modeling; synthesis of asynchronous and dataflow systems; methods and CAD tools for analysis and synthesis of systems, architectures, embedded and high-performance software, and hardware at high-, logic- and physical level; methods and CAD tools for modeling, analysis and optimization of performance, energy consumption, reliability, robustness, safety, security, and testability.

T5: Systems-on-a-chip and networks-on-a-chip
(Heterogeneous) multiprocessor systems on-a-chip (MPSoC), hardware multiprocessors and complex accelerators; generic system platforms and platform-based design; processor, memory and communication architectures; 3D MPSoCs and 3D NoCs; ASIP- and GPU-based platforms; software design and programming models for multicore platforms; IP design, standardization and reuse; parallelism exploitation and scalability techniques; virtual components; system of systems; compiler assisted MPSoCs; hardware support for embedded kernels; embedded software features; static, run-time and dynamic optimizations of embedded MPSoCs; benchmarks and benchmarking for MPSoCs; NoC architecture and quality of service; power dissipation and energy issues in SoCs and NoCs.

T6: Programmable/reconfigurable/adaptable architectures
Design methodologies and tools for reconfigurable computing; run-time, partial and dynamic reconfiguration; fine-grained, mixed-grained and coarse-grained reconfigurable architectures; reconfigurable interconnections and NoCs; FPGAs; systems on reconfigurable chip; system FPGAs, structured ASICs; co-processors; processing arrays; programmable fabrics; adaptive computing devices, systems and software; adaptable ASIPs and ASIP-based MPSoCs; hardware accelerators; optimization of FPGA-based cores; shared resource management; novel models, design algorithms and tools for FPGAs and FPGA-based systems; rapid prototyping systems and platforms; adaptable wireless and mobile systems.

T7: New issues introduced by emerging technologies chnologies
Important issues for system, circuit and embedded software design introduced by e.g. the nanometer CMOS and beyond CMOS technologies, 3D integration, optical and other new memory and communication technologies; new human-machine interfaces; neural- and bio-computation; (bio)sensor and sensor network technologies; pervasive and ubiquitous computing (Internet of Things); related design methods and EDA tools; Flexible Digital Radio-digital architecture design and methodologies concepts for multi-standard, multi-mode flexible radios.

DSD 2016 Committees

GENERAL CHAIR

  • George A. Papadopoulos (University of Cyprus, CY)

PROGRAM CHAIRS

  • Paris Kitsos (TEI West. Greece, GR) - Chair
  • Odysseas Koufopavlou (University of Patras, GR) - Honorary Chair

PUBLICITY CHAIR

  • Nicolas Sklavos, (U of Patras, GR)

PUBLICATION CHAIR

  • Amund Skavhaug, (Norwegian UST, NO)

DSD STEERING COMMITTEE

  • Lech Jozwiak (TU Eindhoven, NL) - Chairman
  • Krzysztof Kuchcinski (U Lund, SE)
  • António Nuñez (IUMA/ULPGC, ES)
  • Francesco Leporati (U Pavia, IT)
  • Eugenio Villar (TEISA U Cantabria, ES)
  • José Silva Matos (U Porto, PT)

DSD PROGRAM COMMITTEE

  • P. Athanas (Virginia Tech, US)
  • H. Basson (U. Littoral, FR)
  • T. Basten (TU Eindhoven, NL)
  • N. Bergmann (U Queensland, AU)
  • C. Bouganis (Imp. Coll., UK)
  • P. Carballo (ULPGC, ES)
  • T. Chen (Colorado St., US)
  • G. Danese (U Pavia, IT)
  • J. Dondo (UCLM, ES)
  • R. Drechsler (U Bremen, DE)
  • L. Fanucci (U Pisa, IT)
  • J. Ferreira (U Porto, PT)
  • M. Figueroa (U Concepcion, CL)
  • K. Gaj (George Mason U, US)
  • P. Gao (Aries Design, US)
  • V. Goulart (U Kyushu, JP)
  • G. Jacquemod (U Nice-Sophia, FR)
  • J. Haid (Infineon, AT)
  • I. Hamzaoglu (U Sabanci, TR)
  • A. Hemani (KTH, SE)
  • D. Houzet (Grenoble IT, FR)
  • M. Hübner (RUB, DE)
  • L. Jozwiak (TU Eindhoven, NL)
  • B. Juurlink (TU Berlin, DE)
  • K. Kent (U New Brunswick, CN)
  • P. Kitsos (TEI of Western Greece, GR)
  • Z. Kotasek, (TU Brno, CZ)
  • H. Kubatova (CTU Prague, CZ)
  • K. Kuchcinski (U Lund, SE)
  • S. Kumar (U Jonkoping, SE)
  • A. Kumar (NUS, SG)
  • A. Lastovetsky (U Coll Dublin, IE)
  • J. Lee (U Chosun, KR)
  • F. Leporati (U Pavia, IT)
  • E. Martins (U Aveiro, PT)
  • J. Matos (U Porto, PT)
  • S. Mosin (Vladimir State U, RU)
  • V. Muthukumar (U Nevada, US)
  • N. Nedjah (U Rio de Janeiro, BR)
  • H. Neto (UT Lisboa, PT)
  • S. Niar (U Valenciennes, FR)
  • D. Noguet (CEA, FR)
  • A. Nuñez (ULPGC, ES)
  • A. Orailoglu (U of California, US)
  • O. Ozturk (U Bilkent, TR)
  • A. Pawlak (ITE&SUT, PL)
  • L. Peng (Louisiana State U, US)
  • T. Pionteck (U Lübeck, DE)
  • A. Postula (U Queensland, AU)
  • Y. Qu (Mediatek, FI)
  • D. Quaglia (U Verona, IT)
  • D. Rossi (U Bologna, IT)
  • J. Sahuquillo (U Pol Valencia, ES)
  • J. Schmidt (CTU Prague, CZ)
  • C. Silvano (Pol Milano, IT)
  • A. Skavhaug (Norwegian UST, NO)
  • N. Sklavos (U Patras, GR)
  • L. Sousa (UT Lisboa, PT)
  • W. Stechele (TU Munich, DE)
  • A. Tokarnia (U Campinas, BR)
  • R. Ubar (IT Tallin, EE)
  • M. Velev (Aries Design, US)
  • H. Vierhaus (BTU Cottbus, DE)
  • T. Villa (U Verona, IT)
  • E. Villar (U Cantabria, ES)
  • S. Vitabile (U. Palermo, IT)
  • C. Wang (USTC, CN)
  • C. Wolinski (IRISA, FR)
  • A. Yurdakul (U Bogazici, TR)

DSD 2016 Submissions

SUBMISSION GUIDELINES

Authors are encouraged to submit their manuscripts to the Easychair System. Should an unexpected web access problem be encountered, please contact the Program Chair.

Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the IEEE format: single-spaced, double column, US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors' names should appear in the manuscript, references included.

Conference Publishing Services (CPS) will publish accepted papers in the conference proceedings and the proceedings will be submitted to the IEEE Xplore Digital library and indexing services.

Extended versions of selected best papers will be published in a special issue of the ISI indexed “Microprocessors and Microsystems: Embedded Hardware Design” Elsevier journal.

DSD 2016 Registration

TBA


Sponsors

UCY