SPECIAL SESSION ON "Dependability, Testing, and Fault Tolerance in Digital Systems (DTFT)"

SPECIAL SESSION SCOPE

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded) digital and mixed hardware/software system engineering. It is a discussion forum for researchers and engineers working on state-of-the-art investigations, developments and applications. It focuses on advanced system design automation concepts, paradigms, methods and tools, as well as modern implementation technologies enabling an effective and efficient development of high-quality systems for demanding applications.

Every designed system has to be tested several times during its life-time - during its design, production, and its in-field operation. The need for testing strictly depends on the actual use of the system, e.g., if the system can be repaired or not, and on the requirements for the system, e.g., if the system must be dependable, fault-tolerant, etc. The design must reflect these requirements. The special session on "Dependability, Testing, and Fault Tolerance in Digital Systems" (DTFT) addresses emerging issues, hot problems, new solution methods and their hardware and software implementations in all fields of digital and analog/mixed-signal system dependability and testing. It is especially focused on testing, dependability, and fault-tolerance of SoC based designs and modern embedded applications.

TOPICS OF INTEREST INCLUDE (BUT ARE NOT LIMITED TO)

• Diagnosis & testing of embedded systems, SoC and NoC testing
• Memory and CPU testing
• Analog, mixed-signal and RF, IDDQ and current testing
• Built-In Self-Test: off-line BIST and on-line BIST, test compression methods
• Testability analysis, synthesis for testability
• Error detection and correction, on-line testing, design of checkers, fault injection techniques
• Design of dependable (robust) circuits and systems, duplex designs, TMR based designs
• Dependability modeling, dependability analysis and validation
• Defect/fault tolerant architectures (SoCs, NoCs, embedded systems)
• FPGA based fault tolerant systems, partial/full reconfiguration based methods
• Formal approaches in fault tolerant systems design
• System diagnosis
• Dependable design in practical applications

SUBMISSION GUIDELINES

Authors are encouraged to submit their manuscripts to the Easychair System. Should an unexpected web access problem be encountered, please contact the Program Chair.

Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the IEEE format: single-spaced, double column, US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors' names should appear in the manuscript, references included.

Conference Publishing Services (CPS) will publish accepted papers in the conference proceedings and the proceedings will be submitted to the IEEE Xplore Digital library and indexing services. Extended versions of selected best papers will be published in a special issue of the ISI indexed “Microprocessors and Microsystems: Embedded Hardware Design” Elsevier journal.

IMPORTANT DATES

• Paper Submission: April 8th 2016 Extended to April 24th
• Notification of Acceptance: May 30th 2016 Extended to June13th
• Camera-ready Paper Due: June 27th 2016 Extended to July 1st

SPECIAL SESSION CHAIRS

H. Kubátová (CTU in Prage, CZ)
Z. Kotásek (BUT, Brno, CZ)

SPECIAL SESSION PROGRAM COMMITTEE

S. Bernard, LIRMM, Montpellier (FR)
Ch. Bolchini, Politechnico di Milano (IT)
A. Bystrov, Newcastle University (UK)
R. Dobai, BUT, Brno (CZ)
A. McEwan, University of Leicester (UK)
G. Fey, Univ. of Bremen (DE)
P. Fišer, CTU in Prague (CZ)
T. Garbolino, Silesian TU, Gliwice (PL)
S. Kajihara, Kyushu Ins. of Tech. (JP)
M. Keim, Mentor Graphics, Wilsonville (US)
Z. Kotásek, BUT, Brno (CZ)
A. Krasniewski, WUT, Warsaw (PL)
H. Kubátová, CTU in Prague (CZ)
I. Levin, Tel Aviv University (IL)
H. Manhaeve, Q-Star Test (BE)
A. Miele, Politecnico di Milano (IT)
G. Di Natale, LIRMM (FR)
A. Orailoglu, UC, San Diego (US)
S. Racek, U. of West Bohemia (CZ)
J. Raik, Tallin U. of Technology (EE)
R. Růžička, BUT, Brno (CZ)
T. Sasao, Meiji University, Kawasaki (JP)
T. Sato, Fukuoka University (JP)
H. Shimada, Nagoya University (JP)
M. Sonza Reorda, Politecnico di Torino (IT)
A. Steininger, Vienna U. of Techn. (AT)
V. Stopjaková, STU, Bratislava (SK)
R. Ubar, TTU, Tallinn (EE)
H. T. Vierhaus, Brandenburg U. Tech. (DE)
Y. Zorian, Virage Logic, CA (US)


CONTACT INFORMATION
Hana Kubátová
Czech Technical University in Prague
Faculty of Information Technology
Department of Digital Design
Thákurova 9, 160 00 Prague 6, Czech Republic
Tel.: +420 224 359 840